Single-phase three-level inverter in open loop

The circuit files for this case are in these two links: circuit_files.tar.gz

This is the first multi-level inverter topology being examined and therefore a simple case to begin with. A single-phase inverter is connected to an LC filter which feeds a resistive load. The main purpose of the simulation is to examine how switching takes place and the effect of changing modulation signals on the output of the inverter bridge.

Before posting the simulation results, the next figure will show the generation of the carrier waves. The frequency of the carrier waves are 4 kHz.

Result 1

The next figure shows the modulation signal superimposed with the carrier waves. The modulation signal is a sinusoidal waveform of peak less than unity and a frequency of 60 Hz.

Result 2

A brief description of the switching of one leg is as follows. These are the switches marked Switch_S1b1, Switch_S2b1, Switch_S3b1 and Switch_S4b1 in the left leg of the inverter bridge.

  1. Switch_S1b1 and Switch_S3b1 are complementary while Switch_S2b1 and Switch_S4b1 are complementary.
  2. Switch_S1b1 will turn on when modulation signal is greater than the upper carrier wave and will turn off when upper carrier wave is greater than the modulation signal. Switch_S2b1 will turn on when modulation signal is greater than lower carrier wave and turn off when lower carrier wave is greater than modulation signal.
  3. For the right leg, the logic will remain the same except that the modulation signal is inverted (*-1).

The next figure shows the generation of switching signals for Switch_S1b1. The switching signals for Switch_S3b1 will be skipped as they are merely a complementary.

Result 3

The next figure shows the generation of switching signals for Switch_S2b1 which is seen to be continuously on for this section of the plot as the modulation signal is always greater than the lower carrier waveform. Switch_S4 will be continuously off.

Result 4

The next figure will show the dc bus voltage, the output voltage of the inverter bridge and the inverter output current. The inverter output voltage shows the multi-level nature of the switching.

Result 5

The next figure show how the modulation signal changes the switching as the modulation index is decreased from 0.9 to 0.7. As can be seen the number of pulses at the highest level decreases as modulation signal decreases.

Result 6

The next figure shows the extreme case when modulation signal drops to 0.4. The third level in the switching voltage disappears.

Result 7

This is the first case of multi-level inverters. The greatest challenge in such a simulation is in ensuring that the simulator is able to deal with cascaded switches, diodes and capacitors correctly.